AN-5048 Datasheet, PDF (1/3 Pages) Fairchild Semiconductor – System Clock Distribution Example Using LVDS

AN-5048
Fairchild Semiconductor
Application Note
August 2002
Revised August 2002
System Clock Distribution Example Using LVDS
Abstract
Noise within high-speed digital systems especially when
dealing with critical signals such as the ones the in clock
distribution circuits can be a concern for designers. Run-
ning single-ended clocks lines over long traces across a
printed circuit board can introduce unwanted noise such as
crosstalk that ultimately affects the performance and reli-
ability of a digital system. This paper will discuss the bene-
fits of using Low Voltage Differential Signaling (LVDS) for
clock distribution and how this signaling technique
addresses this problem. An application example will also
be provided.
Why Use Differential Signaling?
System designers should consider using differential signal-
ing circuits if there is a concern of introducing noise from
clock line(s) across the circuit board and the requirement
for critical clock line with a high level of noise immunity
from the other adjacent PCB traces.
Differential signaling addresses both of these design con-
cerns as the signaling technique uses traces between a
driver and receiver with one trace carrying a positive signal
and the other carrying the negative signal equal and oppo-
site in polarity. With this technique the return current
through the ground system cancels assuming they are
exact opposites of each other. The return current from the
positive signal is (+i) which is equal to the return current of
the negative signal (−i) and their SUM is zero.
Benefits of Using LVDS
A differential receiver is designed to respond to the differ-
ence between a pair of inputs and have a common mode
rejection capability. That means any noise such as EMI or
crosstalk that is common to both traces will be rejected by
the receiver. To illustrate this feature reference Figure 1
which is a scope capture of Fairchild’s FIN1018 single bit
Low Voltage Differential Signaling (LVDS) receiver. The dif-
ferential signals driving 6-inch microstrip lines with ∼400mV
of noise injected equally on both the R− and R+ inputs of
the FIN1018 receiver. Note the TTL output of the receiver
remains in it’s current low state simply ignoring the noise
excursions on its inputs and toggles only after the differen-
tial signals cross over. This common-mode noise rejection
also applies to sources such as power supply variations,
substrate noise, and ground bounce.
FIGURE 1. LVDS Common Noise Rejection Feature
© 2002 Fairchild Semiconductor Corporation AN500801
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