AN-5046 Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – LVDS Receiver Failsafe Biasing Networks

AN-5046
Fairchild Semiconductor
Application Note
August 2002
Revised August 2002
LVDS Receiver Failsafe Biasing Networks
Abstract
Failsafe biasing of an LVDS data line receiver establishes a
know state under certain fault conditions. Typically these
devices are designed with integrated failsafe biasing resis-
tors. This paper will discuss how to add additional external
failsafe biasing resistor networks to increase noise immu-
nity in a system and improve the reliability of failsafe opera-
tion within a specific application. An application example
will be discussed and calculations for resistor values will
also be provided.
External “Assist”
Failsafe Resistors
Certain applications (especially noisy environments) may
warrant the need for additional failsafe protection. Adding
external failsafe resistors may be justified to create a larger
noise margin beyond what is provided by the receiver.
Selecting external failsafe resistors can be done to protect
against differential noise and have minimal impact on the
signal integrity of the LVDS signal. Additional failsafe cur-
rent will tend to “unbalance” the symmetry of the LVDS sig-
nal which should not be an issue at low data rates,
however could be aggravated at higher data rates.
What Resistor Values
Should Be Used?
For Fairchild LVDS receivers designed with an internal fail-
safe bias, they typically will have an internal bias voltage of
≅ 20 to 35mV (Figure 1). In a cable application where the
receiver will not always be driven by the transmitter and
there is a potential for the presence of more than 20mV of
differential noise on the receiver inputs, additional failsafe
resistors should be considered. The resistor values should
be specified to overcome the differential noise and have
minimal impact on the driver current. Figure 1 illustrates a
typical differential input voltage verses the logic output
state of the receiver.
The amount of differential noise anticipated should be
measured and resistor values chosen to overcome this
noise. The VFSB is the offset voltage is generated across
the R^t resistor and the external resistor values should be
enough to overcome the differential noise. Making VFSB
too large will counter with the driver loop current impacting
the signal integrity of the signal. Note using shielded cable
can reduce differential noise.
Once the amount of differential noise at the receiver input
has been determined (under worse case conditions), the
following formulas are provided to assist the designer in
calculating the resistor values.
V_FSB
I_FSB
V_CM
R_t
= R_pu / (R_pu + R_t + R_pd)*V_CC
= V_CC / (R_pu + R_t + R_pd)
(I_FSB < 0.1*I_LOOP)
= (R_up + R_t/2) / (R_pu + R_t + R_pd)*V_CC
(Ideal V_CM ≅ 1.2V)
= (R_t* (R_pu + R_pd)) /(R_pu + R_t + R_pd)
(match R_t to Z_ODIFF)
The external failsafe “Assist” resistors may change the ter-
mination resistance, thus adjust the R_t value to match
within 10% of the characteristic impedance of the transmis-
sion line.
FIGURE 1. Differential Input Voltage verses Receiver Output Voltage
© 2002 Fairchild Semiconductor Corporation AN500799
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