AN-5029 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Interfacing Between PECL and LVDS Differential Technologies

AN-5029
Fairchild Semiconductor
Application Note
August 2002
Revised August 2002
Interfacing Between
PECL and LVDS Differential Technologies
Introduction
Over the past several years, growth in the demand for
high-speed data transmission has spawned dramatic
changes and innovations in high-speed ICs. Achieving
these increased levels of high performance, lower power
and improved noise immunity involves optimizing the inter-
face between ICs. Often times a more cost effective solu-
tion requires interfacing between ICs with different I/O
voltage levels and technology requirements. System
designers must familiarize themselves with the different I/O
circuit configurations to understand the requirements for
proper biasing and effective termination necessary to main-
tain good signal integrity between differing technologies.
This application note will describe an approach to interfac-
ing Positive Emitter Coupled Logic (PECL) with Low Volt-
age Differential Signaling (LVDS) technologies.
What is PECL?
Emitter Coupled Logic (ECL) is an ultra-high speed digital
logic technology and is based on a differential amplifier.
Small signal swings prevent saturation during switching
and increase operating frequency performance. The input
and output voltage levels are referenced directly to V_CC/
V_CCA pins which are normally zero volts or ground potential
operating with a negative V_EE and negative termination
V_TT supplies. With PECL operation the V_CC/V_CCA pins are
offset to the positive +5V nominal potential, V_TT is offset by
+5V from −2V to +3V and the V_EE pin becomes 0V or
ground potential. Refer to the schematic representation of
the PECL operation and the associated voltage levels in
Figure 1.
FIGURE 1. ECL Device Configured for PECL Operation
What is LVDS?
LVDS technology is defined by the ANSI/TIA/EIA-644
industry standard. LVDS is targeted for general purpose
high speed applications requiring very low noise and mini-
mal power consumption. Using a constant current source
driver allows power consumption to be relatively indepen-
dent of frequency resulting in greater performance. LVDS
drivers have a very low differential swing of typically 350
mV, which is centered on an offset voltage of 1.2V above
circuit common (ground). With lower signal swings, higher
data rates can be achieved as it takes less time to transi-
tion between logic states. Noise concerns are reduced with
differential signaling techniques as noise is coupled onto
both conductors with equal magnitude and phase and is
rejected by the receiver, which senses the difference
between the two signals.
TABLE 1. Signal Voltage Comparisons
DC Parameter
Power Supply, V_CC
Output HIGH, V_OH
Output LOW, V_OL
Differential Output, V_OD
Common Mode Voltage, V_OS
5V PECL
+5.0V
4.0V
3.3V
595 to 960 mV
3.65V
LVPECL
3.3V
2.4V
1.7V
595 to 930 mV
2.1V
LVDS
3.3V
1.4V
1.0V
247 to 454 mV
1.2V
© 2002 Fairchild Semiconductor Corporation AN500622
www.fairchildsemi.com