AN-5010 Datasheet, PDF(1/10 Page) Fairchild Semiconductor – IEEE 1284 Interface Design Solutions

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AN-5010 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – IEEE 1284 Interface Design Solutions

AN-5010

Fairchild Semiconductor

Application Note

July 1999

Revised November 2000

IEEE 1284 Interface Design Solutions

Applications note supporting the 74ACT1284, 74VHC161284 and 74LVX161284 devices

Introduction

The IEEE 1284 standard for high speed bi-directional

peripheral data interface allows for significantly higher

(2MB/sec) data throughput than previously possible. Fair-

child Semiconductor offers several devices designed to

support PC and PC peripherals that implement the IEEE

1284 protocol. This applications note discusses the IEEE

1284 standard, Fairchildâs IEEE 1284 transceivers, and

some application examples.

An Advanced Standard Built

on a Legacy Interface

The IEEE 1284-1994 standard, âIEEE Standard Signaling

Method for a Bidirectional Parallel Peripheral Interface for

Personal Computersâ, describes the electrical criteria for

implementing high-speed, bidirectional data transfers using

standard parallel port-based protocols. Until the inception

of IEEE 1284, a standard for bidirectional interface trans-

fers had been absent in the computer industry. Since 1981

the standard parallel port (SPP), also known as the Cen-

tronics port, for PCs and PC peripherals has used a variety

of slow and cumbersome electrical and software configura-

tions. Many SPP applications possess unique implementa-

tions that render them non-standard, incompatible

solutions.

IEEE 1284 describes criteria for asynchronous, inter-

locked, bidirectional data transfers with compatibility to

older SPP modal protocols. Designs that accommodate the

IEEE 1284 protocol have the potential for substantial per-

formance increases. The 1284 standard documents the

requirements that are necessary to create a new and com-

prehensive generation of advanced peripheral devices. As

1284-compliant devices displace older, non-compliant

designs, the antiquated, unidirectional method of transfer-

ring data between the personal computer and peripheral

will disappear.

Interface Modes

Five signaling modes are described in the IEEE 1284 stan-

dard. Three of these -- compatibility, nibble, and byte -- are

SPP-associated legacy modes. The compatibility mode is

supported by 1284-compliant devices and is the basis for

detection and selection of advanced modes. There are two

advanced modes -- enhanced parallel port (EPP) and the

extended capabilities port (ECP). The ECP and EPP

modes were the primary impetus for development of the

IEEE 1284-1994 standard.

The 1284-compliant interface provides:

â¢ Bidirectional extension to the personal computer parallel

port

â¢ Backward compatibility with the older, standard parallel

port (SPP)

â¢ Negotiation to ECP and EPP modes using Compatibility

mode

â¢ Interpretation of signals based on the currently selected

mode of operation

â¢ Increased interface performance

The Advanced Bidirectional Modes

The first truly bidirectional mode, EPP, was co-developed

by Xircom, Inc. and Zenith Data Systems. Intel Corporation

later implemented EPP in its 386SL chipset. EPP was the

first to turn the SPP, also known as the Centronics port, into

a high-speed bidirectional interface. EPP initiates four

types of transfer cycles: data read/write and address read/

write. It also uses asymmetric (level 1), bidirectional signal-

ing driven by a host state machine. The state machine

releases the PCâs processor from directing the interface

negotiation and other signaling chores.

ECP, proposed by Hewlett-Packard and Microsoft, was ini-

tially defined as an advanced method for communicating

with printer and scanner peripherals. Today, a broad variety

of peripherals use the ECP protocol. Unlike the pre-existing

SPP method of combining compatibility and byte modes to

achieve bidirectionality, ECP provides symmetric (level 2)

bidirectional signaling without the requirement of switching

between two modes. Another advantage of ECP is single-

byte, run-length encoding (RLE). When dealing with raster-

ized images, RLE allows compression of identical bytes for

higher data throughput. ECP also uses FIFO (first-in/first-

out) technology and the dynamic memory access (DMA)

system to more efficiently manage data streams.

Significant increases in interface performance are

achieved with ECP and EPP modes. Both modes use half-

duplex data communication whereby information can be

transmitted in either direction, one direction at a time. By

using half-duplex communication, ECP and EPP data

transfer speeds can reach 2MB/s on an ISA bus and

10MB/s on the PCI. This is many times faster than the typi-

cal 150KB/s data transfers that are possible on the SPP.

The ECP and EPP modes require a host hardware state

machine that automatically generates the control strobes

that are necessary for cyclic I/O data transfers. Although

there are differences in how protocols are implemented,

both modes use fully interlocked signaling for word-length

transfers within a single I/O cycle.

In order to attain the greater bandwidths afforded by ECP

and EPP, system designers must insure an interface that is

properly designed. Design imperatives for a 1284-compli-

ant interface include:

1. Preservation of signal fidelity

2. Ability to drive IEEE prescribed 10-meter cable lengths

3. Rejection or reduction of input noise phenomenon

4. Immunity to electrical overstress and ESD (electro-

static discharge)

CROSSVOLTï£ª and FACTï£ª are trademarks of Fairchild Semiconductor Corporation.

www.fairchildsemi.com

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