AN-4153 Datasheet, PDF (1/16 Pages) Fairchild Semiconductor – Designing Asymmetric PWM Half-Bridge Converters

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AN-4153
Designing Asymmetric PWM Half-Bridge Converters with
a Current Doubler and Synchronous Rectifier using
FSFA-Series Fairchild Power Switches (FPS^TM)
Introduction
In general, high-frequency operation allows the use of small-
sized passive components in switch-mode power supplies
(SMPS), though it causes the switching losses to increase in
a hard-switching mode. To reduce switching losses at high
switching frequencies, many soft-switching techniques have
been developed, including load-resonant and zero-voltage-
transition techniques.
Load-resonant techniques use a resonant feature of
capacitors and inductors during the entire switching period
to vary the switching frequency, depending on the input
voltage and load current. The change of the switching
frequency, i.e. pulse frequency modulation (PFM), makes it
difficult to design an SMPS including input filters. Since
there is no output inductor for filtering, the clamped voltage
across output-rectifying diodes allows designers to select
low-voltage-rating diodes. However, the absence of the
output inductor burdens the output capacitors when the load
current increases, making load-resonant techniques
unsuitable for applications with high output current and low
output voltage.
On the other hand, zero-voltage-transition techniques use a
resonant feature between parasitic components during turn-
on and/or turn-off transitions of the switching period. One of
the advantages of these techniques is to use the parasitic
components, such as the leakage inductance of the main
transformer and the output capacitances of the switches, so
there is no need to add more external components to achieve
soft switching. In addition, these techniques take pulse-width
modulation (PWM) up with fixed-switching frequency.
Therefore, these are easier to understand, analyze, and
design than load-resonant techniques.
Due to its simple configuration and zero-voltage switching
(ZVS) characteristic, an asymmetric PWM half-bridge
converter is one of the most popular topologies using the
zero-voltage-transition technique. In addition, the ripple
component of the output current due to an output inductor
becomes small enough to be handled by an appropriate
output capacitor. Being easy to analyze and design and
having an output inductor, it is generally used for
applications with high output current and low output voltage
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
(e.g. game console power supplies). To handle the large
output current, using a synchronous rectifier in the
secondary side is popular to obtain the conduction losses as
ohmic losses instead of diode losses. In addition, a current
doubler increases the utilization of the main transformer
when the output current is high.
Fairchild’s FSFA-series of green power switches (FPS™)
integrates a PWM controller and MOSFETs specifically
designed for asymmetric-controlled topologies with minimal
external components. Compared with discrete-PWM-
controller-and-MOSFETs solutions, FSFA-series switches
can reduce total cost, bill of materials (BOM) list, size, and
weight, while simultaneously increasing efficiency,
productivity, and system reliability.
This application note describes design considerations of an
asymmetric PWM half-bridge converter with current
doubler and synchronous rectifier employing FSFA-series
switches. It includes a step-by-step design procedure as well
as the general features and operational principles of the
proposed topology.
1. Operational Principles of a
Conventional Asymmetric PWM
Half-Bridge Converter
Figure 1 shows a conventional asymmetric PWM half-
bridge converter with a center-tapped transformer. While the
switch S₁ operates with a duty D, depending on the input
voltage and load current, the switch S₂ operates with 1-D.
During DT_S, V_in-V_Cb is applied on the primary side of the
transformer and the secondary diode D₁ turns on. The
primary current i_pri increases since the magnetizing current
i_m of the transformer (not illustrated) and the output inductor
current i_Lo increase together. During (1-D)T_S, V_Cb is applied
on the transformer and D₂ turns on. The capacitor C_b is not
only a voltage source during (1-D)T_S but also a DC-blocking
capacitor to prevent transformer saturation. When the
volt·sec balance for the magnetizing inductance of the
transformer is applied, the following is obtained:
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