AN-248 Datasheet, PDF (1/3 Pages) Fairchild Semiconductor – Electrostatic Discharge Prevention-Input Protection

AN-248
Fairchild Semiconductor
Application Note
October 1987
Revised March 2003
Electrostatic Discharge Prevention-Input Protection
Circuits and Handling Guide for CMOS Devices
Introduction
During the past few years, there have been significant
increase in the usage of low-power CMOS devices in sys-
tem designs. This has resulted in more stringent attention
to handling techniques of these devices, due to their static
sensitivity, than ever before.
All CMOS devices, which are composed of complementary
pairs of N- and P-channel MOSFETs, are susceptible to
damage by the discharge of electrostatic energy between
any two pins. This sensitivity to static charge is due to the
fact that gate input capacitance (5 pF typical) in parallel
with an extremely high input resistance (10¹²â„¦ typical)
lends itself to a high input impedance and hence readily
builds up the electrostatic charges, unless proper precau-
tionary measures are taken. This voltage build-up on the
gate can easily break down the thin (1000Å) gate oxide
insulator beneath the gate metal. Local defects such as
pinholes or lattice defects of gate oxide can substantially
reduce the dielectric strength from a breakdown field of
8–10×10⁶V/cm to 3–4×10⁶V/cm. This then becomes the
limiting factor on how much voltage can be applied safely
to the gates of CMOS devices.
When a higher voltage, resulting from a static discharge, is
applied to the device, permanent damage like a short to
substrate, V_DD pin, V_SS pin, or output can occur. Now static
electricity is always present in any manufacturing environ-
ment. It is generated whenever two different materials are
rubbed together. A person walking across a production
floor can generate a charge of thousands of volts. A person
working at a bench, sliding around on a stool or rubbing his
arms on the work bench can develop a high static potential.
Table 1 shows the results of work done by Speakman¹ on
various static potentials developed in a common environ-
ment. The ambient relative humidity, of course, has a great
effect on the amount of static charge developed, as mois-
ture tends to provide a leakage path to ground and helps
reduce the static charge accumulation.
TABLE 1. Various Voltages Generated in 15%–30%
Relative Humidity (after Speakman¹)
Condition
Person walking across carpet
Person walking across vinyl
floor
Person working at bench
16-lead DIPs in plastic box
16-lead DIPs in plastic shipping
tube
Most
Common
Reading
(Volts)
12,000
4,000
500
3,500
500
Highest
Reading
(Volts)
39,000
13,000
3,000
12,000
3,000
Standard Input Protection
Networks
In order to protect the gate oxide against moderate levels
of electrostatic discharge, protective networks are provided
on all Fairchild CMOS devices, as described below.
Figure 1 shows the standard protection circuit used on all
A, B, and 74C series CMOS devices. The series resistance
of 200Ω using a P⁺ diffusion helps limit the current when
the input is subjected to a high-voltage zap. Associated
with this resistance is a distributed diode network to V_DD
which protects against positive transients. An additional
diode to V_SS helps to shunt negative surges by forward
conduction. Development work is currently being done at
Fairchild on various other input protection schemes.
Diode Breakdown
D₁ = 25V
D₂ = 60V
D₃ = 100V
*These are intrinsic diodes
FIGURE 1. Standard Input Protection Network
© 2003 Fairchild Semiconductor Corporation AN006029
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