AN-1577 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – SG1577A Layout Guidelines

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AN-1577
SG1577A Layout Guidelines
Abstract
This layout is important in high-frequency switching
converter design. If designed improperly, PCB can radiate
excessive noise and contribute to converter instability.
Place the Pulse-Width Modulated (PWM) power stage
components first. Mount all the power components and
connections in the top layer with wide copper areas. The
switchers of buck, inductor, and output capacitor should be
as close to each other as possible to reduce the radiation of
EMI due to the high-frequency current loop. If the output
capacitors are placed in parallel to reduce the ESR of
capacitor, equal sharing ripple current should be considered.
Place the input capacitor near the drain of high-side
MOSFET. In multi-layer PCB, use one layer as power
ground and have a separate control signal ground as the
reference for all signals. To avoid the signal ground being
affected by noise and have best load regulation, it should be
connected to the ground terminal of output.
Checklists for Double-Layer PCB
Follow the below guidelines for best performance:
ƒ A double-layer printed circuit board is recommended.
ƒ Use the bottom layer of the PCB as a ground plane and
make all critical component ground connections through
vias to this layer.
ƒ Keep the traces running from the CLNx terminal to the
output inductor be short.
ƒ Use copper-filled polygons on the top (and bottom, if
two-layer PCB) circuit layers for the CLNx node.
ƒ The small-signal wiring traces from the DLx and DHx
pins to the MOSFET gates should be kept short and
wide enough to easily handle the several amps of drive
current.
ƒ The critical, small-signal components include any
bypass capacitors (SMD-type of capacitors applied at
VCC and SSx/ENB pins), feedback components
(resistor divider), and compensation components
(between INx and COMPx pins). Position those
components close to their pins with a local, clear GND
connection or directly to the ground plane. Keep those
small-signal components and their wiring-traces far
away the noisy generator of CLNx node.
ƒ Place the bootstrap capacitor near the BSTx and CLNx
pins.
ƒ Place the ceramic capacitor (SMD or DIP type) near the
VCC pin and GND pin to gain the noise immunity.
ƒ The resistor on the RT pin should be near this pin and
the GND return should be short and kept away from the
noisy MOSFET GND (which is short together with IC’s
PGND pin to GND plane on back side of PCB).
ƒ Place the compensation components close to the INx
and COMPx pins.
ƒ The feedback resistors for both regulators should be
located as close as possible to the relevant INx pin with
vias tied straight to the ground plane as required.
ƒ Minimize the length of the connections between the
input capacitors, CIN, and the power switchers
(MOSFETs) by placing them nearby.
ƒ Position both the ceramic and bulk input capacitors as
close to the upper MOSFET drain terminal as possible
and make the GND returns (from the source terminal of
lower MOSFET to V_IN capacitor GND) short.
ƒ Position the output inductor and output capacitors
between the upper MOSFET and lower MOSFET and
the load.
ƒ AGND should be on the clearer plane and kept away
from the noisy MOSFET GND.
ƒ PGND should be short, together with MOSFET GND,
then through vias to GND plane on the bottom of PCB.
The best high-current power loop as shown in Figure 1.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 7/31/09
www.fairchildsemi.com