74LVX74_08 Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

February 2008
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
Features
■ Input voltage level translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on
the positive edge of the clock pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
■ LOW input to S_D (Set) sets Q to HIGH level
■ LOW input to C_D (Clear) sets Q to LOW level
■ Clear and Set are independent of clock
■ Simultaneous LOW on C_D and S_D makes both Q and
Q HIGH
Ordering Information
Order
Number
74LVX74M
74LVX74SJ
74LVX74MTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1993 Fairchild Semiconductor Corporation
74LVX74 Rev. 1.4.0
www.fairchildsemi.com