74LVX74 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

May 1993
Revised February 2005
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to S_D (Set) sets Q to HIGH level
LOW input to C_D (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C_D and S_D makes both Q and Q
HIGH
Features
s Input voltage level translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
Package
Number
Package Description
74LVX74M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX74SJ
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX74MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVX74MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
(Note 1)
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
D₁, D₂
CP₁, CP₂
C_D1, C_D2
S_D1, S_D2
Q₁, Q₁, Q₂, Q₂
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
© 2005 Fairchild Semiconductor Corporation DS011606
www.fairchildsemi.com