74LVX273 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – Low Voltage Octal D-Type Flip-Flop

June 1993
Revised April 2005
74LVX273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements. The inputs tolerate up to 7V allowing
interface of 5V systems to 3V systems.
Features
s Input voltage translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX273M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVX273SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D₀–D₇
MR
CP
Q₀–Q₇
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
Truth Table
Operating Mode
Reset (Clear)
Load '1'
Load '0'
H HIGH Voltage Level
L LOW Voltage Level
Inputs
Outputs
MR
CP
D_n
Q_n
L
X
X
L
H

H
H
H

L
L
X Immaterial
LOW-to-HIGH Transition
© 2005 Fairchild Semiconductor Corporation DS011614
www.fairchildsemi.com