74LVX240 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

May 1993
Revised March 2005
74LVX240
Low Voltage Octal Buffer/Line Driver with
3-STATE Outputs
General Description
The LVX240 is an octal inverting buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density. The inputs tolerate up
to 7V allowing interface of 5V systems to 3V systems.
Features
s Input voltage translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX240M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVX240SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX240MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Pin Descriptions
IEEE/IEC
Pin Names
Description
OE₁, OE₂
I₀–I₇
O₀–O₇
3-STATE Output Enable Inputs
Inputs
Outputs
Truth Tables
Connection Diagram
Inputs
OE₁
I_n
L
L
L
H
H
X
Outputs
(Pins 12, 14, 16, 18)
H
L
Z
Inputs
OE₂
I_n
L
L
L
H
H
X
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Outputs
(Pins 3, 5, 7, 9)
H
L
Z
© 2005 Fairchild Semiconductor Corporation DS011609
www.fairchildsemi.com