74LVX161284 Datasheet, PDF (1/11 Pages) Fairchild Semiconductor – Low Voltage IEEE 161284 Translating Transceiver

January 1999
Revised June 2005
74LVX161284
Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (r 14 mA) and are connected to a
separate power supply pin (V_CC-cable) to allow these out-
puts to be driven by a higher supply voltage than the A-
side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the V_CC-cable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A₁–A₈/B₁–B₈ transceiver
pins.
Features
s Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
s Translation capability allows outputs on the cable side to
interface with 5V signals
s All inputs have hysteresis to provide noise margin
s B and Y output resistance optimized to drive external
cable
s B and Y outputs in high impedance mode during power
down
s Inputs and outputs on cable side have internal pull-up
resistors
s Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
s Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Order Number Package Number
Package Description
74LVX161284MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVX161284MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
HD
High Drive Enable Input (Active HIGH)
DIR
Direction Control Input
A₁–A₈
B₁–B₈
A₉–A₁₃
Y₉–Y₁₃
A₁₄–A₁₇
C₁₄–C₁₇
PLH_IN
PLH
Inputs or Outputs
Inputs or Outputs
Inputs
Outputs
Outputs
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
HLH_IN
HLH
Host Logic HIGH Input
Host Logic HIGH Output
© 2005 Fairchild Semiconductor Corporation DS500202
www.fairchildsemi.com