74LVTH573_08 Datasheet, PDF (1/11 Pages) Fairchild Semiconductor – 74LVT573, 74LVTH573 Low Voltage Octal Transparent Latch with 3-STATE Outputs

January 2008
74LVT573, 74LVTH573
Low Voltage Octal Transparent Latch with 3-STATE Outputs
Features
■ Input and output interface capability to systems at
5V V_CC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH573),
also available without bushold feature (74LVT573)
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs source/sink –32mA/+64mA
■ Functionally compatible with the 74 series 573
■ Latch-up performance exceeds 500mA
■ ESD performance:
– Human-body model > 2000V
– Machine model > 200V
– Charged-device model > 1000V
General Description
The LVT573 and LVTH573 consist of eight latches
with 3-STATE outputs for bus organized system applica-
tions. The latches appear transparent to the data when
Latch Enable (LE) is HIGH. When LE is low, the data
satisfying the input timing requirements is latched. Data
appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH, the bus output is in the high
impedance state.
The LVTH573 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal latches are designed for low-voltage (3.3V)
V_CC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT573 and
LVTH573 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Ordering Information
Order Number
74LVT573WM
74LVT573SJ
74LVT573MSA
74LVT573MTC
74LVTH573WM
74LVTH573SJ
74LVTH573MSA
74LVTH573MTC
Package
Number
M20B
M20D
MSA20
MTC20
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation
74LVT573, 74LVTH573 Rev. 1.7.0
www.fairchildsemi.com