74LVQ573_01 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – Low Voltage Octal Latch with 3-STATE Outputs

February 1992
Revised June 2001
74LVQ573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVQ573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The LVQ573 is functionally identical to
the LVQ373 but with inputs and outputs on opposite sides
of the package.
Features
s Ideal for low power/low noise 3.3V applications
s Implements patented EMI reduction circuitry
s Available in SOIC JEDEC, SOIC EIAJ, and QSOP
packages
s Guaranteed simultaneous switching noise level
and dynamic threshold performance
s Improved latch-up immunity
s Guaranteed incident wave switching into 75Ω
s 4 kV minimum ESD immunity
Ordering Code:
Order Number Package Number
Package Description
74LVQ573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVQ573SJ
74LVQ573QSC
M20D
MQA20
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D₀–D₇
LE
OE
O₀–O₇
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Truth Table
Inputs
Outputs
OE
LE
D
O_n
L
H
H
H
L
H
L
L
L
L
X
O₀
H
X
X
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O₀ = Previous O₀ before HIGH-to-LOW transition of Latch Enable
© 2001 Fairchild Semiconductor Corporation DS011361
www.fairchildsemi.com