74LVQ573 Datasheet, PDF (1/6 Pages) STMicroelectronics – OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING

May 1998
74LVQ573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVQ573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output Enable
(OE) inputs. The LVQ573 is functionally identical to the
LVQ373 but with inputs and outputs on opposite sides of the
package.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ, and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75Ω
n 4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ573SC
74LVQ573SJ
74LVQ573QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for
SOIC and QSOP
DS011361-1
IEEE/IEC
DS011361-2
DS011361-3
Pin Descriptions
Pin Names
D₀– D₇
LE
OE
O₀– O₇
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
© 1998 Fairchild Semiconductor Corporation DS011361
www.fairchildsemi.com