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| 74LVQ125 Datasheet, PDF (1/6 Pages) STMicroelectronics – QUAD BUS BUFFERS 3-STATE | |||
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May 1998
74LVQ125
Low Voltage Quad Buffer with 3-STATE Outputs
General Description
The LVQ125 contains four independent non-inverting buffers
with 3-STATE outputs.
Features
n Ideal for low power/low noise 3.3V applications
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Guaranteed pin-to-pin skew AC performance
n Guaranteed incident wave switching into 75â¦
Ordering Code:
Order Number Package Number
Package Description
74LVQ125SC
M14A
14-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC
74LVQ125SJ
M14D
14-Lead Small Outline Package, SOIC EIAJ
Device also available in Tape and Reel. Specify by appending suffix letter âXâ to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Assignment for
SOIC JEDEC and EIAJ
DS011349-1
Pin Descriptions
Pin Names
An, Bn
On
Description
Inputs
Outputs
Truth Table
Inputs
An
Bn
L
L
L
H
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
X = Immaterial
DS011349-2
Output
On
L
H
Z
© 1998 Fairchild Semiconductor Corporation DS011349
www.fairchildsemi.com
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