74LCX74MX Datasheet, PDF (1/14 Pages) Fairchild Semiconductor – Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

March 2008
74LCX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop with 5V Tolerant Inputs
Features
■ 5V tolerant inputs
■ 2.3V–3.6V V_CC specifications provided
■ 7.0ns t_PD max. (V_CC = 3.3V), 10µA I_CC max.
■ Power down high impedance inputs and outputs
■ ±24mA output drive (V_CC = 3.0V)
■ Implements proprietary noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance:
– Human body model > 2000V
– Machine model > 200V
■ Leadless Pb-Free DQFN package
General Description
The LCX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on
the positive edge of the clock pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
■ LOW input to S_D (Set) sets Q to HIGH level
■ LOW input to C_D (Clear) sets Q to LOW level
■ Clear and Set are independent of clock
■ Simultaneous LOW on C_D and S_D makes both Q
and Q HIGH
Ordering Information
Order Number
Package
Number
Package Description
74LCX74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
74LCX74SJ
74LCX74BQX⁽¹⁾
M14D
MLP14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 3.0mm
74LCX74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.0
www.fairchildsemi.com