74LCX646 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – Low Voltage Octal Transceiver/Register with 5V Tolerant Inputs and Outputs

February 1994
Revised March 2001
74LCX646
Low Voltage Octal Transceiver/Register
with 5V Tolerant Inputs and Outputs
General Description
The LCX646 consists of registered bus transceiver circuits,
D-type flip-flops, and control circuitry providing multiplexed
transmission of data directly from the input bus or from the
internal storage registers. Data on the A or B bus will be
loaded into the respective registers on the LOW-to-HIGH
transition of the appropriate pin (CPAB or CPBA) (see
Functional Description).
The LCX646 is designed for low voltage (2.5V or 3.3V) V_CC
applications with capability of interfacing to a 5V signal
environment.
The LCX646 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V − 3.6V V_CC specifications provided
s 7.0 ns t_PD max (V_CC = 3.3V), 10 µA I_CC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (V_CC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V_CC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX646WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LCX646MSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LCX646MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A₀–A₇
B₀–B₇
CPAB, CPBA
SAB, SBA
OE
DIR
Description
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
© 2001 Fairchild Semiconductor Corporation DS011997
www.fairchildsemi.com