74LCX543 Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs

May 1995
Revised March 2001
74LCX543
Low Voltage Octal Registered Transceiver with
5V Tolerant Inputs and Outputs
General Description
The LCX543 is a non-inverting octal transceiver containing
two sets of D-type registers for temporary storage of data
flowing in either direction. Separate Latch Enable and Out-
put Enable inputs are provided for each register to permit
independent input and output control in either direction of
data flow.
The LCX543 is designed for low voltage (2.5V or 3.3V) V_CC
applications with capability of interfacing to a 5V signal
environment.
The LCX543 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V − 3.6V V_CC specifications provided
s 7.0 ns t_PD max (V_CC = 3.3V), 10 µA I_CC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA Output Drive (V_CC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V_CC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX543WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LCX543MSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LCX543MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A₀–A₇
B₀–B₇
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
© 2001 Fairchild Semiconductor Corporation DS012463
www.fairchildsemi.com