74LCX126_08 Datasheet, PDF (1/13 Pages) Fairchild Semiconductor – Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

February 2008
74LCX126
Low Voltage Quad Buffer with 5V Tolerant
Inputs and Outputs
Features
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V V_CC specifications provided
■ 5.5ns t_PD max. (V_CC = 3.3V), 10µA I_CC max.
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal⁽¹⁾
■ ±24mA output drive (V_CC = 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance:
– Human body model > 2000V
– Machine model > 100V
■ Leadless DQFN package
Note:
1. To ensure the high-impedance state during power up
or down, OE should be tied to V_CC through a pull-up
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
General Description
The LCX126 contains four independent non-inverting
buffers with 3-STATE outputs. Each output is disabled
when the associated output-enable (OE) input is LOW.
The inputs tolerate voltages up to 7V allowing the inter-
face of 5V systems to 3V systems.
The 74LCX126 is fabricated with an advanced CMOS
technology to achieve high speed operation while main-
taining CMOS low power dissipation.
Ordering Information
Package
Order Number Number
Package Description
74LCX126M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX126SJ
74LCX126BQX⁽²⁾
M14D
MLP14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX126MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2000 Fairchild Semiconductor Corporation
74LCX126 Rev. 1.5.0
www.fairchildsemi.com