74F51 Datasheet, PDF (1/4 Pages) NXP Semiconductors – Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate

April 1988
Revised July 1999
74F51
Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert Gate
General Description
This device contains two independent logic units, one per-
forming a 2-2 AND-OR-INVERT and the other performing a
3-3 AND-OR-INVERT function.
Ordering Code:
Order Number Package Number
Package Description
74F51SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F51SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F51PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Unit Loading/Fan Out
Pin Names
U.L.
Input I_IH/I_IL
Description
HIGH/LOW Output IOH/IOL
A_n, B_n, C_n, D_n, E_n, F_n Inputs
1.0/1.0 20 µA/−0.6 mA
O_n
Outputs
50/33.3 −1 mA/20 mA
Function Table for 3-Input Gates Function Table for 2-Input Gates
Inputs
Output
Inputs
Output
A₀
B₀
C₀
D₀
E₀
F₀
O₀
H
H
H
X
X
X
L
A₁
B₁
C₁
D₁
O₁
H
H
X
X
L
X
X
X
H
H
H
L
X
X
H
H
L
All other combinations
H
All other combinations
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
© 1999 Fairchild Semiconductor Corporation DS009468
www.fairchildsemi.com