74F37 Datasheet, PDF (1/4 Pages) NXP Semiconductors – Quad 2-input NAND buffer

April 1988
Revised March 1999
74F37
Quad Two-Input NAND Buffer
General Description
This device contains four independent gates, each of which
performs the logic NAND function.
Ordering Code:
Order Number Package Number
Package Description
74F37SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F37SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F37PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Unit Loading/Fan Out
Function Table
Pin Names Description
U.L.
HIGH/LOW
Input I_IH/I_IL
Output I_OH/I_OL
A_n, B_n
O_n
Inputs
Outputs
1.0/2.0 20 µA/−1.2 mA
600/106.6 (80) −12 mA/64 mA
(48 mA)
Inputs
A
B
L
L
L
H
H
L
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
Output
O
H
H
H
L
© 1999 Fairchild Semiconductor Corporation DS009464.prf
www.fairchildsemi.com