74F109 Datasheet, PDF (1/7 Pages) NXP Semiconductors – Positive J-K positive edge-triggered flip-flops

April 1988
Revised November 1999
74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D-type flip-flop (refer
to F74 data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to S_D sets Q to HIGH level
LOW input to C_D sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C_D and S_D makes
both Q and Q HIGH
Ordering Code:
Order Number Package Number
Package Description
74F109SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74F109SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide
74F109PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009471
www.fairchildsemi.com