74ALVC162838 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in the Outputs

November 2001
Revised November 2001
74ALVC162838
Low Voltage 16-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs/Outputs
and 26Ω Series Resistors in the Outputs
General Description
The ALVC162838 contains sixteen non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 16-bit word wide mode. All
outputs can be placed into 3-State through the use of the
OE pin. These devices are ideally suited for buffered or
registered 168 pin and 200 pin SDRAM DIMM memory
modules.
The 74ALVC162838 is designed for low voltage (1.65V to
3.6V) V_CC applications with I/O compatibility up to 3.6V.
The ALVC162838 is also designed with 26Ω series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
The 74ALVC162838 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s Compatible with PC100 and PC133 DIMM module
specifications
s 1.65V–3.6V V_CC supply operation
s 3.6V tolerant inputs and outputs
s 26Ω series resistors in the outputs
s t_PD (CLK to O_n)
4.4 ns max for 3.0V to 3.6V V_CC
5.9 ns max for 2.3V to 2.7V V_CC
9.8 ns max for 1.65V to 1.95V V_CC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V_CC through a pull-up resistor. The minimum
value of the resistor is determined by the current -sourcing capability of the
driver.
Ordering Code:
Ordering Code Package Number
Package Descriptions
74ALVC162838T
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
I₀–I₁₅
O₀–O₁₅
CLK
REGE
Description
Output Enable Input (Active LOW)
Inputs
Outputs
Clock Input
Register Enable Input
© 2001 Fairchild Semiconductor Corporation DS500711
www.fairchildsemi.com