74ACTQ18823 Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – 18-Bit D-Type Flip-Flop with 3-STATE Outputs

September 1991
Revised November 1999
74ACTQ18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ18823 contains eighteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP), Clear (CLR), Clock Enable (EN) and
Output Enable (OE) are common to each byte and can be
shorted together for full 18-bit operation.
The ACTQ18823 utilizes Fairchild’s Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector for
superior performance.
Features
s Utilizes Fairchild’s FACT Quiet Series technology
s Broadside pinout allows for easy board layout
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Separate control logic for each byte
s Extra data width for wider address/data paths or buses
carrying parity
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ18823SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ18823MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE_n
CLR_n
EN_n
CP_n
I₀–I₁₇
O₀–O₁₇
Description
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010953
www.fairchildsemi.com