74ACQ573 Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – Quiet Series Octal Latch with 3-STATE Outputs

January 1990
Revised October 2000
74ACQ573 • 74ACTQ573
Quiet Series Octal Latch with 3-STATE Outputs
General Description
The ACQ/ACTQ573 is a high-speed octal latch with buff-
ered common Latch Enable (LE) and buffered common
Output Enable (OE) inputs. The ACQ/ACTQ573 is func-
tionally identical to the ACQ/ACTQ373 but with inputs and
outputs on opposite sides of the package. The ACQ/ACTQ
utilizes Fairchild’s Quiet Series technology to guarantee
quiet output switching and improved dynamic threshold
performance. FACT Quiet Series features GTO output
control and undershoot corrector in addition to a split
ground bus for superior performance.
Features
s I_CC and I_OZ reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch-up immunity
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Outputs source/sink 24 mA
Ordering Code:
Order Number Package Number
Package Description
74ACQ573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACQ573PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ573QSC
MQA20
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
74ACTQ573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ573PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D₀–D₇
LE
Data Inputs
Latch Enable Input
OE
3-STATE Output Enable Input
O₀–O₇
3-STATE Latch Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation
© 2000 Fairchild Semiconductor Corporation DS010633
www.fairchildsemi.com