74ABT373 Datasheet, PDF (1/11 Pages) Fairchild Semiconductor – Octal Transparent Latch with 3-STATE Outputs

January 1993
Revised March 2005
74ABT373
Octal Transparent Latch with 3-STATE Outputs
General Description
The ABT373 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
Features
s 3-STATE outputs for bus interfacing
s Output sink capability of 64 mA, source capability of
32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT373CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ABT373CSJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT373CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74ABT373CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT373CPC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names
Description
D₀–D₇
LE
Data Inputs
Latch Enable Input (Active HIGH)
OE
Output Enable Input (Active LOW)
O₀–O₇
3-STATE Latch Outputs
© 2005 Fairchild Semiconductor Corporation DS011547
www.fairchildsemi.com