100360 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – Low Power Dual Parity Checker/Generator

March 1998
Revised August 2000
100360
Low Power Dual Parity Checker/Generator
General Description
The 100360 is a dual parity checker/generator. Each half
has nine inputs; the output is HIGH when an even number
of inputs are HIGH. One of the nine inputs (I_a or I_b) has the
shorter through-put delay and is therefore preferred as the
expansion input for generating parity for 16 or more bits.
The 100360 also has a Compare (C) output which allows
the circuit to compare two 8-bit words. The C output is
LOW when the two words match, bit for bit. All inputs have
50 kΩ pull-down resistors.
Features
s Lower power than 100160
s 2000V ESD protection
s Pin/function compatible with 100160
s Voltage compensated operating range = −4.2V to −5.7V
s Min to Max propagation delay 35% tighter than 100160
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100360PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100360QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100360QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
I_a, I_b, I_na, I_nb
Z_a, Z_b
C
Description
Data Inputs
Parity Odd Outputs
Compare Output
Truth Table
(Each Half)
Sum of
HIGH Inputs
Even
Odd
Output
Z
HIGH
LOW
Comparator Function
C = (I_0a ⊕ I_1a) + (I_2a ⊕ I_3a) + (I_4a ⊕ I_5a) + (I_6a ⊕ I_7a) +
(I_0b ⊕ I_1b) + (I_2b ⊕ I_3b) + (I_4b ⊕ I_5b) + (I_6b ⊕ I_7b)
© 2000 Fairchild Semiconductor Corporation DS010611
28-Pin PLCC
www.fairchildsemi.com