100350 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – Low Power Hex D-Type Latch

July 1988
Revised August 2000
100350
Low Power Hex D-Type Latch
General Description
The 100350 contains six D-type latches with true and com-
plement outputs, a pair of common Enables (E_a and E_b),
and a common Master Reset (MR). A Q output follows its D
input when both E_a and E_b are LOW. When either E_a or E_b
(or both) are HIGH, a latch stores the last valid data
present on its D input before E_a or E_b went HIGH. The MR
input overrides all other inputs and makes the Q outputs
LOW. All inputs have 50 kΩ pull-down resistors.
Features
s 20% power reduction of the 100150
s 2000V ESD protection
s Pin/function compatible with 100150
s Voltage compensated operating range = −4.2V to −5.7V
Ordering Code:
Order Number Package Number
Package Description
100350PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100350QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
Description
D₀–D₅
E_a, E_b
MR
Data Inputs
Common Enable Inputs (Active LOW)
Asynchronous Master Reset Input
Q₀–Q₅
Q₀–Q₅
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS009884
28-Pin PLCC
www.fairchildsemi.com