100331 Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – Low Power Triple D Flip-Flop

February 1990
Revised August 2000
100331
Low Power Triple D-Type Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP_C), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP_n),
Direct Set (SD_n) and Direct Clear (CD_n) inputs. Data enters
a master when both CP_n and CP_C are LOW and transfers
to a slave when CP_n or CP_C (or both) go HIGH. The Master
Set, Master Reset and individual CD_n and SD_n inputs over-
ride the Clock inputs. All inputs have 50 kΩ pull-down
resistors.
Features
s 35% power reduction of the 100131
s 2000V ESD protection
s Pin/function compatible with 100131
s Voltage compensated operating range = −4.2V to −5.7V
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100331SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100331PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100331QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100331QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
CP₀–CP₂
CP_C
D₀–D₂
CD₀–CD₂
SD_n
MR
MS
Q₀-Q₂
Q₀–Q₂
Description
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS010262
28-Pin PLCC
www.fairchildsemi.com