100302 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Low Power Quint 2-Input OR/NOR Gate

August 1989
Revised August 2000
100302
Low Power Quint 2-Input OR/NOR Gate
General Description
The 100302 is a monolithic quint 2-input OR/NOR gate with
common enable. All inputs have 50 kΩ pull-down resistors
and all outputs are buffered.
Features
s 43% power reduction of the 100102
s 2000V ESD protection
s Pin/function compatible with 100102
s Voltage compensated operating range = −4.2V to −5.7V
s Available to industrial grade temperature range
(PLCC package only)
Ordering Code:
Order Number Package Number
Package Description
100302SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100302PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100302QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100302QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Pin Descriptions
Pin Names
D_na–D_ne
E
O_a–O_e
O_a–O_e
Description
Data Inputs
Enable Input
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS010580
www.fairchildsemi.com