XR81111 Datasheet, PDF (9/12 Pages) Exar Corporation – Universal Clock - High Frequency LVPECL Clock Synthesizer

XR81111
Application Information
Functional Truth Table
The XR81111-CA04 has two frequency select pins,
FSLEL[1:0], that determine the output frequency from the
device. With the two FSEL inputs, one of 4 different clock
rates can be selected. This allows the XR81111-CA04 to
support a variety of applications such as PCI Express,
Ethernet, SAS and 10GE for example. If the FSEL pins are
left floating, the XR81111-CA04 will default (with internal
pull-down resistors on the FSEL inputs) to the 100MHz out-
put configuration.
Table 1: Output Frequency Selection
FSEL[1:0]
00
01
10
11
XTAL
(MHz)
25
25
25
25
Output Frequency
(MHz)
Applications
100
125
150
156.25
PCI Express
Ethernet
SAS
10GE, XAUI
2.5V
LVPECL
Output
2.5V
2.5V
:
:
50:
LVPECL
Input
50:
:
:
Figure 6: XR81111 2.5V LVPECL Output Termination
VCC
LVPECL
Output
VCC
50:
LVPECL
Input
50:
50:
50:
Termination for LVPECL Outputs
The termination schemes shown in Figure 5 and Figure 6
are typical for LVPECL outputs. Matched impedance layout
techniques should be used for the LVPECL output pairs to
minimize any distortion that could impact your maximum
operating frequency. Figure 7 is an alternate termination
scheme that uses a Y-termination approach.
3.3V
LVPECL
Output
3.3V
3.3V
130:
130:
50:
LVPECL
Input
50:
82:
82:
For 3.3V systems RTT= 50:
For 2.5V systems RTT= 19:
RTT
Figure 7: XR81111 Alternate LVPECL Output Termination
Using Y-termination
Output Signal Timing Definitions
The following diagrams clarify the common definitions of
the AC timing measurements.
Q
nQ
tcycle n
tcycle n+1
tjit(cc) = |tcycle n - tcycle n+1| (over 1000 cycles)
Figure 5: XR81111 3.3V LVPECL Output Termination
Figure 8: Cycle-to-Cycle Jitter
© 2014 Exar Corporation
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