XR16V2751 Datasheet, PDF (9/52 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE

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REV. P1.0.0
PRELIMINARY
XR16V2751
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE
2.3 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 17). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
2.4 Device Identification and Revision
The XR16V2751 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DLM will provide
0x0A for the XR16V2751 and reading the content of DLL will provide the revision of the part; for example, a
reading of 0x01 means revision A.
2.5 Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a
logic 0 on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send
transmit data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power
up initialization to write to the same internal registers, but do not attempt to read from both UARTs
simultaneously. Individual channel select functions are shown in Table 1.
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE
CSA#
1
0
1
0
CSB#
1
1
0
0
FUNCTION
UART de-selected
Channel A selected
Channel B selected
Channel A and B selected
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the 2751 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in
the Motorola Bus Mode. See Table 2.
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE
CS# A3
1
N/A
0
0
0
1
FUNCTION
UART de-selected
Channel A selected
Channel B selected
2.6 Channel A and B Internal Registers
Each UART channel in the V2751 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM/DLD), and a user accessible Scratchpad Register (SPR).
Beyond the general 16C2550 features and capabilities, the V2751 offers enhanced feature registers (EMSR,
FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow
control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO
trigger level control, and FIFO level counters. All the register functions are discussed in full detail later in
“Section 3.0, UART INTERNAL REGISTERS” on page 22.
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