English
Language : 

XR32430EUCRTR-F Datasheet, PDF (8/14 Pages) Exar Corporation – 3-Driver/5-Receiver Intelligent RS-232 Transceiver with 1.65V-5.5V Interface
XR32430/XR32431
Application Information
General Description
The XR32430/31 transceiver meets the EIA/TIA-232 and
ITU-T V.28/V.24 communication protocols and can be
implemented in battery-powered, portable, or hand-held
applications such as notebook or laptop computers. The
XR32430/31 device features Exar's proprietary and pat-
ented (U.S. 5,306,954) on-board charge pump circuitry that
generates ±5.5V RS-232 voltage levels from a single +3.0V
to +5.5V power supply. The XR32430/31EU and XR32430/
31EH devices can operate at a data rate of 1000Kbps and
460Kbps fully loaded while the XR32430/31EB devices fea-
ture slew-rate limited outputs for reduced crosstalk and
EMI.
The XR32430/31 is a 3-driver/5-receiver device, ideal for
portable or hand-held applications.
The XR32430/31 is an ideal choice for power sensitive
designs. The XR32430/31 devices feature AUTO ON-
LINE® circuitry which reduces the power supply drain to a
1μA supply current. The XR32430/31 includes one comple-
mentary receiver that remains alert to monitor an external
device’s Ring Indicator while the XR32430/31 is shutdown.
In many portable or hand-held applications, an RS-232
cable can be disconnected or a connected peripheral can
be turned off. Under these conditions, the internal charge
pump and the drivers will be shut down. Otherwise, the sys-
tem automatically comes on line. This feature allows design
engineers to address power saving concerns without major
design changes.
Theory of Operation
The XR32430/31 series is made up of four basic circuit
blocks:
1. Drivers
2. Receivers
3. The Exar proprietary charge pump, and
4. AUTO ON-LINE® circuitry.
Drivers
The drivers are inverting level transmitters that convert TTL
or CMOS logic levels to 5.0V EIA/TIA-232 levels with an
inverted sense relative to the input logic levels. Typically,
the RS-232 output voltage swing is ±5.5V with no load and
±5V minimum fully loaded. The driver outputs are protected
against infinite short-circuits to ground without degradation
in reliability. These drivers comply with the EIA-TIA-232-F
and all previous RS-232 versions. Unused drivers inputs
should be connected to GND or VCC/VL.
The drivers have a minimum data rate of 250kbps
(XR32430/31EB), 460Kbps (XR32430/31EH) or 1Mbps
(XR32430/31EU) fully loaded.
Receivers
The receivers convert +5.0V EIA/TIA-232 levels to TTL or
CMOS logic output levels. Receivers are High-Z when the
AUTO ON-LINE® circuitry is enabled and activated or when
in shutdown. The truth table logic of the XR32430/31 driver
and receiver outputs can be found in Table 2 on page 11.
Since receiver input is usually from a transmission line
where long cable lengths and system interference can
degrade the signal, the inputs have a typical hysteresis
margin of 300mV. This ensures that the receiver is virtually
immune to noisy transmission lines. Should an input be left
unconnected, an internal 5KΩ pull-down resistor to ground
will commit the output of the receiver to a HIGH state.
Charge Pump
The charge pump is a Exar–patented design (U.S.
5,306,954) and uses a unique approach compared to older
less–efficient designs. The charge pump still requires four
external capacitors, but uses a four–phase voltage shifting
technique to attain symmetrical ±5.5V power supplies. The
internal power supply consists of a regulated dual charge
pump that provides output voltages of ±5.5V regardless of
the input voltage (VCC) over the +3.0V to +5.5V range. This
is important to maintain compliant RS-232 levels regardless
of power supply fluctuations.
The charge pump operates in a discontinuous mode using
an internal oscillator. If the output voltages are less than a
magnitude of ±5.5V, the charge pump is enabled. If the out-
put voltages exceed a magnitude of 5.5V, the charge pump
is disabled. This oscillator controls the four phases of the
voltage shifting. A description of each phase follows.
Phase 1
V- charge storage — During this phase of the clock cycle,
the positive side of capacitors C1 and C2 are initially
charged to VCC. C1+ is then switched to GND and the
charge in C1– is transferred to C2–. Since C2+ is con-
nected to VCC, the voltage potential across capacitor C2 is
now 2 times VCC.
© 2014 Exar Corporation
8 / 13
exar.com/XR32430_XR32431
Rev 1A