XR-T6166 Datasheet, PDF (8/16 Pages) Exar Corporation – Codirectional Digital Data Processor

XR-T6166
SYSTEM DESCRIPTION
Transmitter
Figure 1 shows the XR-T6166 transmitter section block
diagram. The transmitter converts eight bit bursts or
octets of 2.048Mbps serial data present in a PCM
time-slot to a coded continuous 64kbps data stream.
During operation, data input is controlled by external
clock and time-slot signals, and the 64kbps data output is
timed by an external 256kHz clock. Since the input and
output rates may not be exactly equal because of slight
clock rate differences, periodic slips can occur.
Therefore, circuitry is included to delete or repeat octets, if
necessary. Transmitter operation is as follows.
PCM data is applied to PCMIN (pin 19), a 2.048MHz local
clock is applied to TX2MHz (pin 20), and a time-slot signal
is applied through the time-slot multiplexer. This
multiplexer allows the transmitter to be hard wired to two
time-slot positions. A time-slot signal is applied to
multiplexer inputs TS1T (pin 10) or TS2T (pin 12), and a
time-slot select logic level is applied to TTSEL (pin 15). A
high level at TTSEL selects TS1T while a low level
enables TS2T. The time-slot is an envelope derived
externally from TX2MHz that covers eight clock pulses.
The rising edge of the time-slot signal should be made to
coincide with the falling edge of TX2MHz. Eight bits of
PCM data are clocked into the transmitter input register
on the rising edge of TX2MHz while the selected time-slot
signal is high. The input register data is then transferred
to a storage latch.
Transmission of 64kbps data is controlled by the 256kHz
local clock that is applied to TX256kHz (pin 17). It is not
necessary for this clock to be synchronized with any other
signals that are applied to the transmitter. The output
process begins by transferring data from the storage latch
to the output shift register after transmission of the
previous eight bits of data is complete. Four periods of
TX256kHz are required to encode each data bit. A “logic
0” applied to PCMIN is coded as 0101 while a “logic 1” is
coded as 0011. This data is output on either T+R (pin 13)
or T-R (pin 14) according to the AMI (alternate mark
inversion) coding rule. Note that the T+R and T-R outputs
as well as the corresponding XR-T6164 transmitter inputs
(TX+I/P, TX-I/P) are all active-low. Therefore, a “logic 0” is
coded as a 1010 and a “logic 1” as a 1100 at the bipolar
transmitter output as specified by CCITT G.703.
Transmission of octet timing is performed by feeding the
seventh and eighth data bits in each word to the same
transmitter output. This function may be inhibited by
setting ALARMIN (pin 16) high to transmit an alarm
condition.
Should skew occur between the TX2MHz and TX256kHz
clocks signals, or during an adjustment of the timing of the
time-slot signal, circuitry is included to delete or repeat
complete words of data. This could happen, for example,
when changing from one time-slot position to another.
Outputs are provided to indicate when a data byte is
inserted or deleted. A byte repetition or insertion occurs
once if no new PCM data is received. The BIT flag (pin 18)
is active during the transmission of inserted data. A byte
repetition just occurs once. If no new PCM data is
received, the T+R and T-R outputs stay high. A byte
deletion occurs when the transmitter receives a new byte
of data before the previous byte is transferred from the
storage latch to the output register. Under this condition,
the stored data is overwritten and the BDT flag (pin 11) is
active.
Receiver
Figure 2 shows the block diagram of the XR-T6166
receiver section. The receiver converts coded continuous
64kbps data to eight bit bursts of 2.048Mbps serial data
suitable for insertion in a PCM time-slot. During
operation, data input is timed by a clock that is extracted
from the input signal, while output is controlled by external
locally supplied clock and time-slot signals. Since the
data input and output rates may not be exactly equal,
circuitry is included to delete or repeat eight bit data
blocks, if necessary. Receiver operation is as follows.
A line interface chip such as the receive section of the
XR-T6164 converts the encoded bipolar 64kbps signal to
dual-rail active-low logic levels. These signals are
applied to the XR-T6166 receiver S+R (pin 2) and S-R
(pin 3) inputs. A 128kHz clock, which is derived from the
received signal, is used to decode this data, and then to
clock it into one of two storage registers. Two registers
are used so that one may be receiving continuous data at
64kbps while the other is sending eight bit bursts at a
2.048Mbps rate to PCMOUT (pin 28) while the receiver
time-slot signal is high. The time-slot is an envelope
derived externally from RX2MHz (pin 5) that covers eight
clock pulses. The rising edge of the time-slot signal
should be made to coincide with the rising edge of
RX2MHz. Eight bits of PCM data are clocked out of the
receiver register on the rising edge of RX2MHz while the
Rev. 2.02
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