SP3203ECY-L Datasheet, PDF (8/16 Pages) Exar Corporation – 3V RS-232 Serial Transceiver with Logic Selector and 15kV ESD Protection

Device: SP3203E
SHUTDOWN T_XOUT R_XOUT
0
High-Z High-Z
1
Active Active
Charge
Pump
Inactive
Active
Table 2. SHUTDOWN Truth Tables
(Note: When the device is shutdown, the SP3203E's
charge pump is turned off and V+ decays to Vcc, V- is
pulled to ground and the transmitter outputs are disabled
as High Impedance.)
The charge pump operates in a discontinu-
ous mode using an internal oscillator. If the
output voltages are less than a magnitude
of 5.5V, the charge pump is enabled. If the
output voltages exceed a magnitude of 5.5V,
the charge pump is disabled. This oscillator
controls the four phases of the voltage shift-
ing. A description of each phase follows.
Phase 1
— V_SS charge storage — During this phase
of the clock cycle, the positive side of capaci-
tCo_lr₊sisCth_{1 eanndswCit2cahreed}
initially charged
to GND and the
to V_CC.
charge
in C_1– is transferred to C_2–. Since C₂₊ is con-
nected to V_CC, the voltage potential across
capacitor C₂ is now 2 times V_CC.
Phase 2
— V_SS transfer — Phase two of the clock
connects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of
C₂ to GND. This transfers a negative gener-
ated voltage to C₃. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the volt-
age to C₃, the positive side of capacitor C₁
is switched to V_CC and the negative side is
connected to GND.
Phase 3
— V_DD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C₁ produces –V_CC in
the negative terminal of C₁, which is applied
tCo₂₊thiseanteVg_Ca_Ct,ivtheesvidoeltaogfecappoatecnittoiarlCa_{2c.roSsisncCe2}
is 2 times V_CC.
Phase 4
— V_DD transfer — The fourth phase of
the clock connects the negative terminal
of C₂ to GND, and transfers this positive
generated voltage across C₂ to C₄, the
V_DD storage capacitor. This voltage is
regulated to +5.5V. At this voltage, the in-
ternal oscillator is disabled. Simultaneous
with the transfer of the voltage to C₄, the
positive side of capacitor C₁ is switched to V_CC
and the negative side is switched to GND, al-
lowing the charge pump cycle to begin again.
The charge pump cycle will continue as long
as the operational conditions for the internal
oscillator are present.
Since both V⁺ and V^– are separately gener-
ated
and
from
V^– will
V_CC, in a no–load
be symmetrical.
condition V⁺
Older charge
pump approaches that generate V^– from
V⁺ will show a decrease in the magnitude
of V^– compared to V⁺ due to the inherent
inefficiencies in the design.
V_L Supply Level
+3V to +5V
+
C5 0.1µF
1 _C1+
+
C1 0.1µF
3 C1-
4 C2+
+
C2 0.1µF
5 C2-
19
VCC
SP3203E
V+ ²
V- ⁶
TTL/CMOS
INPUTS
T₁IN
T_XIN
T₁OUT
T_XOUT
+
C3 0.1µF
C4 0.1µF
+
TTL/CMOS
OUTPUTS
R₁OUT
R₁IN
5KΩ
VCC
R_XOUT
20 _SHUTDOWN
R_XIN
5KΩ
1000pF
1000pF
GND
18
12
VL
+3V to +5.5V
Figure 2. Loopback Test Circuit for RS-232 Driver
Data Transmission Rates
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • www.exar.com

SP3203E_100_120810