XRS10L220 Datasheet, PDF (7/38 Pages) Exar Corporation – SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR

EXSTOR - 1 XRS10L220
REV. 1.02
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
3.0 FUNCTIONAL DESCRIPTION
A top-level view of the XRS10L220 is shown in Figure 3 outlining the interfaces to the device and the required
support components. The data path can be seen at the top of the device. This includes the two output transmit
and input receive paths at the top left, providing the upstream interface to the host, and the two output transmit
and input receive paths at the top right, providing the downstream interface to the target devices. The clocking,
control, and configuration interfaces are shown below the dotted line.
FIGURE 3. XRS10L220 INTERFACES
Serial ATA Upstream
Interface to HBAs
S IT _P /N [1 :0 ]
SIR_P/N[1:0]
S O T _ P /N [1 :0 ]
S O R _ P /N [1:0 ]
Serial ATA Downstream
Interface to Devices
Control and
Status
Interface
C o n fig u ra tio n
Interface
VDDA
Calibration Resistor
49.9 Ω ± 0.5%
DRACT[1:0] CMU_REF_P/N
HBACT
P S _ S ID E B A N D _ B
PORTSEL
RESETB
XOD
XOG
PWRDNB
TCK
MDC
M D IO
TDI
TDO
TMS
R B IA S
TRST
Reference Clock
C rystal O scillator I/O
JTAG
Interface
The XRS10L220 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This
common building block provides a uniform implementation with common characteristics and a common
register map, but provides a functional implementation of independent PHY blocks. Digital logic
implementations of Serial ATA link layer blocks along with port selector and port multiplier logic provide the
remainder of the data path within the XRS10L220. In addition, management and control interfaces including an
MDIO interface for register control, a JTAG interface for boundary scan purposes, and a resistor calibration
circuit complete the device. A block diagram of the XRS10L220 is shown in Figure 4.
FIGURE 4. XRS10L220 BLOCK DIAGRAM
SIR0
SATA II
SIT0
3G PHY
SIR1
SATA II
SIT1
3G PHY
SATA II
LINK
LAYER
PORT
SELECTOR
RATE
ADJUST
FIFO
SATA II
LINK
LAYER
PORT
MULTIPLIER
SATA II
LINK
LAYER
SATA II
3G PHY
SOT0
SOR0
SATA II
3G PHY
SOT1
SOR1
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