SP332 Datasheet, PDF (7/11 Pages) Sipex Corporation – RS-232/RS-485 Multi-Mode Serial Transceiver

Phase 3
— V_DD charge storage — The third phase
of the clock is identical to the first phase
— the charge transferred in C₁ produces
–5V in the negative terminal of C₁, which
is applied to the negative side of capacitor
C₂. Since C₂₊ is at +5V, the voltage potential
across C₂ is l0V.
Phase 4
— V_DD transfer — The fourth phase of the
clock connects the negative terminal of C₂
to ground and transfers the generated l0V
across C₂ to C₄, the V_DD storage capacitor.
Again, simultaneously with this, the positive
side of capacitor C₁ is switched to +5V and
the negative side is connected to ground,
and the cycle begins again.
Since both V+ and V^– are separately gen-
erated from V_CC in a no–load condition, V+
and V^– will be symmetrical. Older charge
pump approaches that generate V^– from
V+ will show a decrease in the magnitude
of V^– compared to V+ due to the inherent
inefficiencies in the design.
The clock rate for the charge pump typically
operates at 15kHz. The external capaci-
tors must be 0.1µF with a 16V breakdown
rating.
+10V
a) C2+
GND
GND
b) C2-
-10V
Figure 7. Charge Pump Waveforms
V_CC = +5V
+10V
+
C_{1 –}
+
C_{2 –}
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
V_CC = +5V
+
C_{1 –}
–5V
+5V
+
C_{2 –}
–5V
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
Figure 8. Charge Pump Phase 1.
Figure 9. Charge Pump Phase 3.
V_CC = +5V
V_CC = +5V
C₄
+
+
+ – _{VDD Storage Capacitor}
C_{1 –}
C_{2 –}
– + _{VSS Storage Capacitor}
–10V
C₃
+
C_{1 –}
–5V
+5V
+
C_{2 –}
–5V
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
Figure 10. Charge Pump Phase 2.
Figure 11. Charge Pump Phase 4.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com

SP332_100_012610