XRK697H73 Datasheet, PDF (6/12 Pages) Exar Corporation – 1:12 LVCMOS PLL CLOCK GENERATOR

XRK697H73
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
TABLE 5: AC CHARACTERISTICS (CON’T) (V_DD = 3.3V +/- 5%)
SYMBOL
CHARACTERISTICS
CONDITION
t_PLZ, t_PHZ
Output Disable Time
t_PZL, t_PZH
Output Enable Time
t_JIT(CC)
Cycle-to-Cycle Jitter
All outputs in same divider
config.
t_JIT(PER)
Period Jitter
All outputs in same divider
config.
t_JIT(Ø)
I/O Phase Jitter RMS (1 σ)
VCO = 400MHz
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
BW
PLL closed loop bandwidth
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
t_LOCK
PLL Lock Time
NOTES:
a. PLL locked, except when configured in bypass mode.
b. t_(Ø)[s] = t_(Ø)[°] ÷ (fref x 360°)
c. Not including Qsync output
d. T is the output period.
FIGURE 3. TEST LOAD
MIN
TYP
MAX
8
8
150
200
150
11
86
13
88
16
19
21
22
27
30
1.20-3.5
0.70-2.50
0.50-1.80
0.45-1.20
0.30-1.00
0.25-0.70
0.20-0.55
0.17-0.40
0.12-0.30
0.11-0.28
10
UNIT
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ms
Transmission Line
Z = 50Ω
50Ω
V_TT
6