XRD64L44 Datasheet, PDF (6/15 Pages) Exar Corporation – Dual 10-Bit 50MSPS CMOS ADC

XRD64L44
Preliminary
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
Test Conditions (Unless Otherwise Specified)
T_A = 25°C AV_DD = DV_DD = +3.3V, VIN = GND to +2.5V, V_RLF = GND, V_RHF = +2.5V and Fs = 50 MSPS, 50% Duty
Cycle, Differential Input Mode
Symbol Parameter
Min. Typ. Max. Unit Conditions/Comments
DC ACCURACY
DNL
Differential Non-Linearity
-1.0 +/-0.4 1.0 LSB
INL
Integral Non-Linearity
+/-1.1
LSB
MON Monotonicity
No Missing Codes
Guaranteed by Test
FSE
Full Scale Error
+10
mV F.S. = (VRHF - VRLF)x0.97
ZSE
Zero Scale Error
ANALOG INPUT
5
mV Single Ended Mode
INVR Input Voltage Range
0
VRHFx0.97 V VRLF Grounded
INRES Input Resistance
20
KOhms
INCAP Input Capacitance
5
pF
INBW Input Bandwidth
400
MHz -1dB Small Signal
REFERENCE INPUT, INTERNAL BANDGAP REFERENCE AND REFERENCE BUFFER
RLAD Ladder Resistance
100 125 150 Ohms
RLADTCO Ladder Resistance Tempco
+0.8
Ohms/°C
VBG
Bandgap Output Voltage Range
1.25
V
VBGTC Bandgap Reference Tempco
30
ppm/°C
VRLF
0.0
2.0
V
VRHF
VRLF+1.0
AVdd-0.6 V Internal Reference Buffer
VRHF External Reference
VRLF+1.0
AVdd V External
VRHF PSRR Internal Reference Buffer
6
mV/V
CONVERSION and TIMING CHARACTERISTICS (C_L = 10pF)
MAXCON Maximum Conversion Rate
50 60
MINCON Minimum Conversion Rate
100
PDEL Pipeline Delay(Latency)
t
Aperture Delay Time
4
ad
APJT Aperture Jitter Time
12
t
Digital Output Rise Time
3
r
t
Digital Output Fall Time
3
f
t_pd
Output Data Propagation Delay
6
t
Output Data Enable Delay
6
den
t
Output Data Disable Delay
5
dis
CLKDC Clock Duty Cycle
40 50
MSPS
KSPS
17 CLK Clock Cycles Digital Data Delay
ns
ps Peak-to Peak
ns
ns
14 ns Guaranteed by Design
14 ns Guaranteed by Design
ns
60 % Guaranteed by Design
Rev. P1.00
6