XR81102 Datasheet, PDF (6/8 Pages) Exar Corporation – Universal Clock - High Frequency LVPECL Clock Synthesizer

XR81102
Application Information
Termination for LVPECL Outputs
The termination schemes shown in Figure 2 and Figure 3
are typical for LVPECL outputs. Matched impedance layout
techniques should be used for the LVPECL output pairs to
minimize any distortion that could impact your maximum
operating frequency. Figure 4 is an alternate termination
scheme that uses a Y-termination approach.
3.3V
LVPECL
Output
3.3V
3.3V
130:
130:
50:
LVPECL
Input
50:
82:
82:
Output Signal Timing Definitions
The following diagrams clarify the common definitions of
the AC timing measurements.
Q
nQ
tcycle n
tcycle n+1
tjit(cc) = |tcycle n - tcycle n+1| (over 1000 cycles)
Figure 5: Cycle-to-Cycle Jitter
Figure 2: XR81102 3.3V LVPECL Output Termination
2.5V
LVPECL
Output
2.5V
2.5V
:
:
50:
LVPECL
Input
50:
:
:
Figure 3: XR81102 2.5V LVPECL Output Termination
VCC
VCC
LVPECL
Output
50:
LVPECL
Input
50:
50:
50:
For 3.3V systems RTT= 50:
For 2.5V systems RTT= 19:
RTT
Figure 4: XR81102 Alternate LVPECL Output Termination
Using Y-termination
Q
80%
20%
nQ
t_R
80%
V_SWING
20%
t_F
Figure 6: Output Rise/Fall Time and Swing
Q
nQ
t_PW
t_PERIOD
odc =
t_PW
t_PERIOD
x 100%
Figure 7: Output Period and Duty Cycle
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