XR81101 Datasheet, PDF (6/8 Pages) Exar Corporation – Universal Clock - High Frequency LVCMOS Clock Synthesizer

XR81101
Application Information
Termination for LVCMOS Outputs
The termination schemes shown in Figure 2 and Figure 3
are typical for LVCMOS outputs. A split supply approach
can be used utilizing the scope’s internal 50: impedance,
as shown in Figure 4.
3.3V ± 5%
LVCMOS
Output
Z = 50:
3.3V ± 5%
100:
100 :
High Impedance
scope probe
Output Signal Timing Definitions
The following diagrams clarify the common definitions of
the AC timing measurements.
80%
LVCMOS
Output
20%
80%
20%
t_R
t_F
Figure 5: Cycle-to-Cycle Jitter
Figure 2: XR81101 3.3V LVCMOS Output Termination
2.5V ± 5%
LVCMOS
Output
Z = 50:
2.5V ± 5%
100:
:
High Impedance
scope probe
LVCMOS
Output
V_CC/2
t_PW
t_Period
Odc = ^tPW
t_Period
100%
Figure 6: Output Rise/Fall Time
Figure 3: XR81101 2.5V LVCMOS Output Termination
+Vcc/2 ± 5%
Vcc
LVCMOS
Output
Vss
-Vcc/2 ± 5%
Z = 50:
:
Scope
Figure 4: XR81101 Split Supply LVCMOS Output Termination
© 2014 Exar Corporation
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exar.com/XR81101
Rev 1A