ST16C2450_05 Datasheet, PDF (6/30 Pages) Exar Corporation – 2.97V TO 5.5V DUART

ST16C2450
2.97V TO 5.5V DUART
xr
REV. 4.0.1
FIGURE 3. ST16C2450 DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
CSA#
CSB#
INTA
INTB
VCC
UART
Channel A
TXA
RXA
DTRA#
RTSA#
CTSA#
DSRA#
CDA#
RIA#
OP2A#
UART
Channel B
TXB
RXB
DTRB#
RTSB#
CTSB#
DSRB#
CDB#
RIB#
OP2B#
RESET
GND
VCC
RS-232 Serial Interface
RS-232 Serial Interface
.
2.2 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 8). An active high pulse of at least 40 ns duration will be required to activate the reset function
in the device.
2.3 Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,
but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
Table 1.
TABLE 1: CHANNEL A AND B SELECT
CSA#
1
0
1
0
CSB#
1
1
0
0
FUNCTION
UART de-selected
Channel A selected
Channel B selected
Channel A and B selected
2.4 Channel A and B Internal Registers
Each UART channel in the 2450 has a standard register set for controlling, monitoring and data loading and
unloading. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scratch pad register
(SPR).
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