XR19L202IL48-0B Datasheet, PDF (50/50 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

XR19L202
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 25
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 25
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 25
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 27
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 27
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 28
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 29
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 30
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 31
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 32
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ......................................................................................... 32
TABLE 12: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 32
TABLE 13: AUTO RTS HYSTERESIS ................................................................................................................................................ 33
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY............................................................................................. 33
4.13 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD) - READ/WRITE ....................................... 33
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY....................................................................... 33
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY ................................................................................. 34
4.16 TRIGGER LEVEL REGISTER (TRG) - WRITE-ONLY .................................................................................... 34
4.17 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY ....................................................................... 34
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE........................................................................... 34
TABLE 14: TRIGGER TABLE SELECT ................................................................................................................................................ 34
4.19 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 35
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 35
4.19.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 36
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 37
ABSOLUTE MAXIMUM RATINGS.................................................................................. 38
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 38
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 40
Unless otherwise noted: TA=-40o to +85oC, Vcc=3.3 - 5.5V, 70 pF load where applicable .................................... 40
FIGURE 11. CLOCK TIMING............................................................................................................................................................. 41
FIGURE 12. MODEM INPUT/OUTPUT TIMING .................................................................................................................................... 42
FIGURE 13. 16 MODE (INTEL) DATA BUS READ TIMING ................................................................................................................... 43
FIGURE 14. 16 MODE (INTEL) DATA BUS WRITE TIMING.................................................................................................................. 43
FIGURE 15. 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 44
FIGURE 16. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING......................................................................................................... 44
FIGURE 17. RECEIVE READY INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................... 45
FIGURE 18. TRANSMIT READY INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................. 45
FIGURE 19. RECEIVE READY INTERRUPT TIMING [FIFO MODE] ....................................................................................................... 46
FIGURE 20. TRANSMIT READY INTERRUPT TIMING [FIFO MODE] ..................................................................................................... 46
PACKAGE DIMENSIONS (48 PIN QFN - 7 X 7 X 0.9 mm) .............................................. 47
REVISION HISTORY...................................................................................................................................... 48
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