XRT83D10 Datasheet, PDF (5/18 Pages) Exar Corporation – SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT

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SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
XRT83D10
REV. 1.0.3
CONTROL FUNCTION
PIN #
NAME
2
ICT
16
ExCLK
11
TAOS
9
LOOPB
10
LOOPA
13
FOFS
TYPE
I
I
I
I
DESCRIPTION
In Circuit Testing
When this pin is tied "Low" all output pins are forced to high-impedance state
for in-circuit testing.
NOTE: Internally pulled up.
External Clock Input:
DS1 (1.544 MHz ± 130 ppm) or CEPT E1 (2.048 MHz ± 80 ppm) clock signal is
provided. ExCLK must be an independent clock to guarantee device perfor-
mance for all specifications. This clock must be continuously active (ungapped
or unswitched) and void of jitter for the device to operate properly.
Transmit All Ones:
With this pin tied "High", an AMI encoded all "1’s" signal sent to the transmit
output using ExCLK as the timing reference. A remote loop back has higher
priority over TAOS request.
NOTE: Internally pulled down.
Loopback control.
LOOPB along with LOOPA is used for selecting different loopbacks.
LOOPA
0
0
1
1
LOOPB
0
1
0
1
Loopback Mode
Normal Operation
Digital
Remote
Local
NOTE: Internally Pulled down.
I
Loopback control.
LOOPB along with LOOPA is used for selecting different loopbacks.
NOTE: Internally Pulled down.
O
FIFO Overflow Signal:
This pin is set "High" if the phase jitter of the incoming signal exceeds the toler-
ance of the jitter attenuator’s buffer. This may result in loss of data and Jitter
Attenuator is no longer attenuating jitter.
POWER AND GROUND
PIN #
NAME
3
AVDD
4
AGND
24
DVDD
26
DGND
TYPE
****
****
****
****
DESCRIPTION
Analog Supply: 5V ± 5% or 3.3V ± 5%
Analog GND.
Digital Supply: 5V ± 5% or 3.3V ± 5%
Digital GND
5