XRK69773 Datasheet, PDF (5/12 Pages) Exar Corporation – 1:12 LVCMOS PLL CLOCK GENERATOR

REV. P1.0.0
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
TABLE 4: AC CHARACTERISTICS (V_DD = 3.3V +/- 5%)
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
f_REF
Input reference frequency^a
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
PLL bypass mode
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
6.25
5.00
120
80.0
60.0
48.0
40.0
30.0
24.0
20.0
15.0
12.0
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
f_VCO
VCO frequency range
200
480
MHz
f_MAX
Output frequency^a
÷2 output
÷4 output
÷6 output
÷8 output
÷10 output
÷12 output
÷16 output
÷20 output
÷24 output
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
240.0
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
f_{STOP_CLK} Serial interface frequency
20.0
MHz
V_PP
Peak to Peak Input Voltage
LVPECL
400
PECL and PECL
1000
mV
V_CMR Common Mode Range PECL
LVPECL
1.2
and PECL
V_DD - 0.9
V
t_PW
CLKx pulse width
2.0
ns
It_R, It_F
Input CLKx Rise/Fall time
0.8V to 2.0V
1
ns
t_(∅)
Propagation Delay (static 6.25MHz < f_REF < 65.0MHz
-3
phase offset) CLKx to FB_IN^b _{65.0MHz < fREF < 125MHz}
-4
f_REF = 50MHz & FB = ÷8
-166
+3
°
+4
°
+166
ps
t_SK(O)
Output to output skew
Bank A (QAx to QAy)
Bank B (QBx to QBy)
Bank C (QCx to QCy)
all outputs (QXy to QWz)^c
100
ps
100
ps
100
ps
250
ps
DC
Output duty cycle^d
(T÷2)-200 T÷2 (T÷2)+200 ps
Ot_R, Ot_F
Output Rise/Fall time
0.55 to 2.4V
0.1
1.0
ns
5