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XR-T7296 Datasheet, PDF (5/16 Pages) Exar Corporation – DS3/STS-1, E3 Integrated Line Transmitter
XR-T7296
ELECTRICAL CHARACTERISTICS (See Figure 8 )
Test Conditions: VDD = 5V $5%, TA = -40°C to +85°C, unless otherwise specified. All timing characteristics
are measured with 10pF loading.
Symbol
Parameter
Min.
Typ.
Max.
Units
AC Electrical Characteristics
TCLK Clock Duty Cycle (DS3 / STS-1)
45
50
55
%
TCLK Clock Duty Cycle (E3)
47
50
53
%
tR
TCLK Clock Rise Time (10% to 90%)
4.0
ns
tF
TCLK Clock Fall Time (10% to 90%)
4.0
ns
tTSU
TPDATA/TNDATA to TCLK Falling Set Up Time
4.0
ns
tTHO TPDATA/TNDATA to TCLK Falling Hold Time
5.0
ns
tTDY
TTIP/TRING to TCLK Rising Propagation Delay 1
0.6
14
ns
RCLK Clock Duty Cycle
45
50
55
%
tR
RCLK Clock Rise Time (10% to 90%)
4.0
ns
tF
RCLK Clock Fall Time (10% to 90%)
4.0
ns
tRSU RPDATA/RNDATA to RCLK Falling Set Up Time
4.0
ns
tRHO RPDATA/RNDATA to RCLK Falling Hold Time
5.0
ns
tR
RCLKO Clock Rise Time (10% to 90%)
4.0
ns
tF
RCLKO Clock Fall Time (10% to 90%)
4.0
ns
tRDY
RPOS/RNEG/RNRZ to RCLKO Rising Propagation
Delay 2
4.0
ns
DC Electrical Characteristics
VDDD,
VDDA
DC Supply Voltage
Supply Current 3
4.75
5
5.25
V
133
mA
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage IOUT=-4.0mA
VOH
Output High Voltage IOUT=3.0mA
IL
Input Leakage Current 4
Pin 19/20/26 (Input=0V)
0
VDD* 0.7
GNDD
VDDD - 0.5
-50
0.5
V
VDDD
V
0.4
V
VDDD
V
$10
µA
-150
µA
CI
Input Capacitance
CL
Load Capacitance
10
pF
10
pF
Notes:
1 When the encoder is enabled, a handling delay of four and a half TCLK clock cycles for B3ZS and five and half clock cycles for HDB3
always exists between TPDATA/TNDATA and TTIP/TRING. The handling delay is reduced to two clock cycles when the encoder
is disabled.
2 When the decoder is enabled, a handling delay of six and a half RCLK clock cycles will always exist between RPDATA/RNDATA
and RPOS/RNEG/RNRZ. The handling delay is reduced to one and half RCLK clock cycles when the decoder is disabled.
3 Supply current is measured with transmitter sending all ones AMI signal and with Transmit Level (TXLEV) set to high.
4 All inputs except pin 19, 20 and pin 26.
Specifications are subject to change without notice
Rev. 2.01
5