SP211EEA-L-TR Datasheet, PDF (5/15 Pages) Exar Corporation – 5V RS-232 Serial Transceivers

FEATURES
The SP206/207/208/211 multi-channel RS-232
line transceivers provide a variety of configu-
rations to fit most communication needs, es-
pecially those applications where +/-12V is not
available. All models in this series feature low-
power CMOS construction and Exar's proprie-
tary on-board charge pump circuitry to generate
the +/-10V RS-232 voltage levels. The ability to
use 0.1µF charge pump capacitors saves board
space and reduces circuit cost. Different mod-
els within the series provide different driver/re-
ceiver combinations to match any application
requirement.
The SP206 and SP211 models feature a low-
power shutdown mode that reduces power sup-
ply drain to 1µA.
The models in this series are available in 24-pin
and 28-pin SO (wide) and SSOP (shrink) small
outline packages. Devices can be specified for
commercial (0ºC to +70ºC) or industrial/extend-
ed (-40ºC to +85ºC) operating temperatures.
Theory Of Operation
Charge pump
The charge pump is an Exar patented design
and uses a unique approach compared to older
less-efficient designs. The charge pump still
requires four external capacitors, but uses a
four phase voltage shifting technique to attain
symmetrical +/-10V power supplies. Figure 1a
shows the waveform found on the positive side
of capacitor C2 and Figure 3b shows the nega-
tive side of capacitor C2. There is a free-run-
ning oscillator that controls the four phases of
the voltage shifting. A description of each phase
follows:
Phase 1
Vss charge storage - During this phase of the
clock cycle, the positive side of capacitors C1
and C2 are initially charged to +5V. C1+ is then
switched to ground and the charge in C1- is
transferred to C2-. Since C2+ is connected to
+5V, the voltage potential across capacitor C2
is now 10V.
Phase 2
DESCRIPTION
Vss transfer: Phase two of the clock connects
the negative terminal of C2 to the Vss stor-
age capacitor and the positive terminal of C2
to ground, and transfers the generated -10V to
C3. Simultaneously, the positive side of capaci-
tor C1 is switched to +5V and the negative side
is connected to ground.
Phase 3
Vdd charge storage: The third phase of the
clock is identical to the first phase. The charge
transferred in C1 produces -5V in the negative
terminal of C1, which is applied to the negative
side of C2. Since C2+ is at +5V, the voltage po-
tential across C2 is 10V.
Phase 4
Vdd transfer: The fourth phase of the clock con-
nects the negative terminal of C2 to ground,
and transfers the generated 10V across C2 to
C4, the Vdd storage capacitor. Again, simulta-
neously with this, the positive side of capaci-
tor C1 is switched to +5V and the negative side
is connected to ground, and the cycle begins
again.
Since both V+ and V- are separately generated
from Vcc; in a no-load condition V+ and V- will
be symmetrical. Older charge pump approach-
es that generate V- from V+ will show a de-
crease in magnitude of V- compared to V+ due
to the inherent inefficiencies in the design.
The clock rate for the charge pump typically op-
erates at greater than 15kHz allowing the pump
to run efficiently with small 0.1uF capacitors
with a 16V breakdown voltage rating.
The SP206/207/208/211 devices are made up
of three basic circuit blocks - 1) transmitter/
driver, 2) receiver and 3) charge pump. Each
model within the series incorporates variations
of these circuit to achieve the desired configu-
ration and performance.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • Fax [phone] • www.exar.com SP206, 207, 208, 211_101_060111