XR16L2550_07 Datasheet, PDF (46/46 Pages) Exar Corporation – LOW VOLTAGE DUART WITH 16-BYTE FIFO

XR16L2550
REV. 1.1.2
xr
LOW VOLTAGE DUART WITH 16-BYTE FIFO
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 24
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 24
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 24
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 25
TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION ................................................................................................................... 26
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 26
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 27
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 27
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 28
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 29
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 30
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 30
4.12 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 30
4.13 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 31
4.14 ENHANCED FEATURE REGISTER (EFR) .................................................................................................. 31
TABLE 12: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 31
4.15 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 32
TABLE 13: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 33
ABSOLUTE MAXIMUM RATINGS...................................................................................34
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 34
ELECTRICAL CHARACTERISTICS ................................................................................34
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................34
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................35
Unless otherwise noted: TA=-40o to +85oC, Vcc is 2.25V to 5.5V, .......................................................................... 35
70 pF load where applicable...................................................................................................................................... 35
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 36
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 36
FIGURE 17. DATA BUS WRITE TIMING............................................................................................................................................. 37
FIGURE 16. DATA BUS READ TIMING .............................................................................................................................................. 37
FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 38
FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 38
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 39
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 39
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B............................ 40
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 40
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)...............................................41
PACKAGE DIMENSIONS (44 PIN PLCC) .......................................................................42
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 MM)..............................................43
REVISION HISTORY.......................................................................................................................................44
TABLE OF CONTENTS ............................................................................................................ I
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