XRT94L33_1 Datasheet, PDF (45/110 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER ATM/PPP - HARWARE MANUAL

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XRT94L33
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AC14
STS1TXA_CK_2
IO
TXSENDFCS_2
TXGFCCLK_2
TTL
CMOS
CMOS
STS-1 Transmit Telecom Bus Clock Input pin/Transmit
HDLC Control Block Send FCS Command Input pin –
Channel 2:
The exact function of this input pin depends upon whether the
STS-1 Telecom Bus Interface for Channel 2 has been enabled
or not.
If STS-1 Telecom Bus (Channel 2) has been enabled –
STS1TXA_CLK_2 – “STS-1 Transmit Telecom Bus” Transmit
Clock Input – Channel 2:
This input clock signal functions as the clock source for the
STS-1 Transmit Telecom Bus, associated with Channel 2. All
input
signals,
(e.g.,
STS1TXA_ALARM_2,
STS1TXA_D_2[7:0]”, STS1TXA_DP_2, STS1TXA_PL_2,
STS1TXA_C1J1_2) are sampled upon the falling edge of this
input clock signal.
This clock signal should operate at 19.44MHz. (For STS-3
mode) or 6.48MHz (for STS-1 mode)
If STS-1 Telecom Bus (Channel 1) has NOT been enabled:
If STS-1 Telecom Bus (Channel 1) has not been enabled, then
this particular pin can be configured to function in either of the
following roles.
TXSENDFCS_2 (Transmit HDLC Controller block Send
FCS Command Input – High Speed HDLC Controller Mode
Only)
The user’s terminal equipment is expected to control both this
input pin and the “TXSENDMSG_2” input pin during the
construction and transmission of each outbound HDLC frame.
This input pin permits the user to command the Transmit
HDLC Controller block to compute and insert the computed
FCS value into the back-end of the “outbound” HDLC frame as
a trailer.
If the user has configured the Transmit HDLC Controller to
compute and insert a CRC-16 value into the “outbound” HDLC
frame, then the terminal equipment is expected to pull this
input pin “high” for two periods of TxHDLCClk_2.
Likewise, if the user has configured the Transmit HDLC
Controller to compute and insert a CRC-32 value into the
“outbound” HDLC frame, then the terminal equipment is
expected to pull this input pin “high” for four periods of
TxHDLCClk_2.
TXGFCCLK_2 (Transmit GFC Nibble-Field Input Port clock
signal Input) – ATM Applications ONLY.
This pin only functions in this particular role if the XRT94L33
has been configured to operate in the ATM UNI Mode.
NOTE: The user should tie this pin to GND if the DS3/E3
Framer block has NOT been configured to operate in the
“High-Speed HDLC Controller” Mode.
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